Analog-to-digital converters (ADCs) are employed in a variety of electronic systems including computer modems, wireless telephones, satellite receivers, process control systems, etc. Such systems demand cost-effective ADCs that can efficiently convert an analog input signal to a digital output signal over a wide range of frequencies and signal magnitudes with minimal noise and distortion.
An ADC typically converts an analog signal to a digital signal by sampling the analog signal at pre-determined sampling intervals and generating a sequence of binary numbers via a quantizer, wherein the sequence of binary numbers is a digital representation of the sampled analog signal. Some of the commonly used types of ADCs include integrating ADCs, Flash ADCs, pipelined ADCs, successive approximation register ADCs, Delta-Sigma (ΔΣ) ADCs, two-step ADCs, etc. Of these various types, the pipelined ADCs and the ΔΣ ADCs are particularly popular in applications requiring higher resolutions.
A ΔΣ ADC employs over-sampling, noise-shaping, digital filtering and digital decimation techniques to provide high resolution analog-to-digital conversion. One popular design of a ΔΣ ADC is multi-stage noise shaping (MASH) ΔΣ ADC. A MASH ΔΣ ADC is based on cascading multiple first-order or second-order ΔΣ ADCs to realize high-order noise shaping. An implementation of a MASH ΔΣ ADC is well known to those of ordinary skill in the art.
While a ΔΣ ADCs generally provide improved signal-to-noise ratio, improved stability, etc., comparator offsets in the single-bit or multi-bit quantizer of a ΔΣ ADC lead to increased distortion levels due to errors caused by the offsets. Generally speaking, the mechanism that causes distortion levels in ΔΣ ADCs to increase due to comparator offsets occurs when the comparator offsets are too high. Subsequent ADC stages will overload when trying to quantize the output of the preceding stage resulting in a failure to reproduce the output of the first stage due to overloading and clipping. Overloading leads to faulty digital recombination, and quantization error from the first stage quantizer will not be cancelled by digital recombination logic. Furthermore, this leads to leakage of the first stage quantization noise to the recombined output resulting in an increased noise floor and spurious components.
To achieve a ΔΣ ADC with low nonlinear distortion, a high tolerance to comparator offsets is desired.